The present invention relates to a semiconductor device; and, more particularly, to a redundancy circuit in a semiconductor memory device.
In general, a semiconductor memory device undergoes a predetermined test in a wafer state so that undesired cells, word lines, bit lines or the like having errors or defects therein are sort out. Furthermore, the same test is also carried out for a redundancy circuit in order to find out defects. As is well known, the redundancy cell array is required in the semiconductor memory device in order for a cell in the redundancy cell array to perform a normal operation in place of an arbitrary cell in a normal cell array, if the arbitrary cell in the normal cell array cannot perform its function for any reason.
FIG. 1 is a block diagram setting forth a prior art redundancy circuit and FIG. 2 is a timing diagram representing operation of the prior art redundancy circuit.
Herein, a fuse set controller 110 is configured with a fuse set for storing a set of address signals and a controller for controlling the set of address signals.
Referring to FIGS. 1 and 2, in order to test for finding out defects in a predetermined redundancy circuit, a redundancy test signal RED_TEST is applied to the fuse set controller 110 so that the redundancy circuit goes into a test mode after a T2 period. The fuse set controller 110 outputs a redundancy enable signal REDEN<0:3> of logic high level according to a predetermined combination of applied address signals ADDRESS. Afterwards, when a selection control signal SEL_CTRL is applied to a redundant selector 120 while the redundancy enable signal REDEN<0:3> is applied thereto, the redundant selector 120 outputs a redundant selection signal RED_SEL<0:3>. Herein, a T1 period corresponds to an operation time for setting the redundancy circuit and a period between the T1 and the T2 is correspondent to a normal operation time of the redundancy circuit.
However, since one redundant substitution unit is arranged in one fuse set according to the prior art redundancy circuit, there is a drawback that it is impossible to utilize the fuse set if there is any defect in the redundant substitution unit. Meanwhile, although semiconductor memory devices have become smaller as process technology has become more enhanced, an occupation area of the fuse set in the device is still relatively large so that it is difficult to implement a highly integrated device, wherein another problem arises.